An intelligent partitioning approach of the system-on-chip for flexible and stretchable systems

被引:0
作者
Changqing Xu
Yi Liu
Yintang Yang
机构
[1] Xidian University,School of Microelectronics
来源
Science China Information Sciences | 2018年 / 61卷
关键词
functional module clustering; cluster mapping; SoC; flexible and stretchable systems;
D O I
暂无
中图分类号
学科分类号
摘要
In this paper, we propose an intelligent partitioning approach of the system-on-chip (SoC) to improve the bendability and stretchability of flexible and stretchable systems. The proposed approach partitions the SoC intelligently into clusters of functional modules according to the communication flows and area constraint. Based on the communication volume between clusters, a heuristic algorithm is applied to map these clusters onto the 2D mesh network-on-chip (NoC) for co-optimization of communication energy and delay. Experimental results show that our approach can effectively partition the SoC into small ICs of the same size. The approach also reduces power consumption and communication delay by 10.64%–56.63% and 15.06%–50.30%, respectively.
引用
收藏
相关论文
共 21 条
[1]  
Sekitani T(2010)Flexible organic transistors and circuits with extreme bending stability Nat Mater 9 1015-1022
[2]  
Zschieschang U(2008)Stretchable and foldable silicon integrated circuits Science 320 507-511
[3]  
Klauk H(2008)From the cover: materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations Proc Natl Acad Sci USA 105 18675-18680
[4]  
Kim D H(2008)Ultrathin silicon solar microcells for semitransparent, mechanically flexible and microconcentrator module designs Nat Mater 7 907-915
[5]  
Ahn J H(2009)Flexible electronics: ultrathin silicon circuits with strain-isolation layers and mesh layouts for high-performance electronics on fabric, vinyl, leather, and paper Adv Mater 21 3703-3707
[6]  
Choi W M(2015)An efficient application mapping approach for the co-optimization of reliability, energy, and performance in reconfigurable NoC architectures IEEE Trans Comput-Aided Des Integr Circ Syst 34 1264-1277
[7]  
Kim D H(2010)SunFloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips IEEE Trans Comput-Aided Des Integr Circ Syst 29 1987-2000
[8]  
Song J(undefined)undefined undefined undefined undefined-undefined
[9]  
Choi W M(undefined)undefined undefined undefined undefined-undefined
[10]  
Yoon J(undefined)undefined undefined undefined undefined-undefined