A Mapping Framework Based on Packing for Design Space Exploration of Heterogeneous MPSoCs

The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to satisfy this demand. But to be able to take advantage of these systems, new strategies are required to map applications to such a system and to evaluate the systems performance at a very early design stage. We will present a framework for static, analytical, bottom-up temporal and spatial mapping of applications to MPSoCs based on packing. This mapping framework allows easy performance evaluation and design space exploration of heterogeneous systems on chip.