Design of power-efficient CMOS based oscillator circuit with varactor tuning control

被引：0
作者：
Dileep Dwivedi
Manoj Kumar
Vandana Niranjan
机构：
[1] University School of Information,Communication and Technology
[2] Guru Gobind Singh Indraprastha University,Department of ECE
[3] Indira Gandhi Delhi Technical University for Women,undefined
来源：
SN Applied Sciences | 2021年 / 3卷
关键词：
Delay cell; I-MOS varactor; MOS current mode logic; Phase noise; Voltage controlled oscillator;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This paper presents a low-power, wide tuning range CMOS voltage-controlled oscillator with MCML (MOS current mode logic) differential delay cell. Voltage controlled oscillator (VCO) circuit is designed in TSMC 0.25 μm CMOS process. To achieve the broad frequency range concept of variable capacitance is employed in the proposed VCO circuit. Source/drain tuning voltage (Vtune) and body bias voltage (Vb) of I-MOS varactor are used to achieve variable capacitance at different I-MOS varactor widths (W). The dual control voltage of I-MOS varactor results in a tuning range from 0.528 GHz to 2.014 GHz. VCO's figure of merit (FoM) is 152.13 dBc/Hz with phase noise of −93.77 dBc/Hz at 1 MHz offset from the oscillation frequency. The proposed VCO dissipates maximum power of 3.127 mW.
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