Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application

Capricious digital filter (CDF) plays a significant role of signal processing application field to eradicate noise. Any prototype filter desired frequency response is attained by developing all pass makeover-based capricious digital filter (APM-CDF) that sustains full control on cutoff frequency. The benefits of APM-CDF are limited through its speed, area, and power consume. In this manuscript, Baugh–Wooley multiplier (BWM) with error reduced carry prediction approximate adder (ERCPAA) is proposed to accelerate the filter design, decreasing the area and power consume. ERCPAA is a rapid binary adder that takes low power and area. ERCPAA adder is separated as 3 blocks: approximate full adder cells, carry prediction logic, constant truncation including error diminishing logic, these reduce power with area. BWM is utilized to decrease the hardware complex including high speed, lesser area, and lesser power consume. The proposed filter is applicable in ECG signal noise removing applications to offer filtered higher-quality signals. The proposed filter is implemented in Verilog and simulation is activated in Xilinx ISE 14.5 tool. The simulation outcomes shows lesser delay 32.87%, 26.88%, and 32.88%, and lower area 20%, 80%, and 65% comparing to the existing filters, like partial product adding in Vedic design-ripple carry adder model FIR filter for electrocardiogram signal denoising algorithm (DF-4VM-CSA), Vedic design-carry look ahead (VMD-CLA), respectively. The proposed filter is activated in MATLAB/Simulink for reading input ECG signal. Finally, the proposed filter attains 34.86%, 26.98% higher SNR analyzed to the existing filters, like DF-4VM-CSA, DF-VMD-CLA, respectively.