Novel Optimum Parity-Preserving Reversible Multiplier Circuits

Reversible logic is considered as a basic requirement for designing quantum computers. Reversible circuits do not waste energy. The use of this logic in low-power complementary metal–oxide–semiconductor circuits, quantum computing, and DNA computing has rendered reversible logic integral in today’s technology. Multiplication is regarded as a major operation in the arithmetic. Herein, four optimized parity-preserving reversible signed and unsigned multiplier circuits are presented to reduce the QUANTUM COST of the circuits. The designs can be expanded to an N × N dimension. We prove that these multiplier circuits have lower QUANTUM COST, CONSTANT INPUTs, and GARBAGE OUTPUTs compared with previous studies.