A survey of FPGA-based accelerators for convolutional neural networks

被引：3
|
作者：
Sparsh Mittal
机构：
[1] Indian Institute of Technology,Department of Computer Science and Engineering
来源：
Neural Computing and Applications | 2020年 / 32卷
关键词：
Deep learning; Neural network (NN); Convolutional NN (CNN); Binarized NN; Hardware architecture for machine learning; FPGA; Reconfigurable computing; Parallelization; Low power;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Deep convolutional neural networks (CNNs) have recently shown very high accuracy in a wide range of cognitive tasks, and due to this, they have received significant interest from the researchers. Given the high computational demands of CNNs, custom hardware accelerators are vital for boosting their performance. The high energy efficiency, computing capabilities and reconfigurability of FPGA make it a promising platform for hardware acceleration of CNNs. In this paper, we present a survey of techniques for implementing and optimizing CNN algorithms on FPGA. We organize the works in several categories to bring out their similarities and differences. This paper is expected to be useful for researchers in the area of artificial intelligence, hardware architecture and system design.
引用
收藏
页码：1109 / 1139
页数：30
相关论文
共 50 条
  • [41] High Energy Efficiency FPGA-based Accelerator for Convolutional Neural Networks Using Weight Combination
    Shu, Chenghao
    Pang, Wei
    Liu, Hao
    Lu, Shengli
    2019 IEEE 4TH INTERNATIONAL CONFERENCE ON SIGNAL AND IMAGE PROCESSING (ICSIP 2019), 2019, : 578 - 582
  • [42] Calculation Optimization for Convolutional Neural Networks and FPGA-based Accelerator Design Using the Parameters Sparsity
    Liu Qinrang
    Liu Chongyang
    JOURNAL OF ELECTRONICS & INFORMATION TECHNOLOGY, 2018, 40 (06) : 1368 - 1374
  • [43] FPGA-Based Training of Convolutional Neural Networks With a Reduced Precision Floating-Point Library
    DiCecco, Roberto
    Sun, Lin
    Chow, Paul
    2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT), 2017, : 239 - 242
  • [44] A High-efficiency FPGA-based Accelerator for Convolutional Neural Networks using Winograd Algorithm
    Huang, Y.
    Shen, J.
    Wang, Z.
    Wen, M.
    Zhang, C.
    2018 INTERNATIONAL CONFERENCE ON ELECTRONICS, COMMUNICATIONS AND CONTROL ENGINEERING (ICECC), 2018, 1026
  • [45] MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks
    Wu, Chen
    Zhuang, Jinming
    Wang, Kun
    He, Lei
    2021 31ST INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2021), 2021, : 33 - 37
  • [46] Energy-Efficient and High-Throughput FPGA-based Accelerator for Convolutional Neural Networks
    Feng, Gan
    Hu, Zuyi
    Chen, Song
    Wu, Feng
    2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2016, : 624 - 626
  • [47] Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights
    Duan, Yunzhi
    Li, Shuai
    Zhang, Ruipeng
    Wang, Qi
    Chen, Jienan
    Sobelman, Gerald E.
    2018 IEEE 23RD INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP), 2018,
  • [48] Implementation of FPGA-based Accelerator for Deep Neural Networks
    Tsai, Tsung-Han
    Ho, Yuan-Chen
    Sheu, Ming-Hwa
    2019 IEEE 22ND INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2019,
  • [49] DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family
    Wang, Ying
    Xu, Jie
    Han, Yinhe
    Li, Huawei
    Li, Xiaowei
    2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2016,
  • [50] FPGA-Based Reconfigurable Convolutional Neural Network Accelerator Using Sparse and Convolutional Optimization
    Gowda, Kavitha Malali Vishveshwarappa
    Madhavan, Sowmya
    Rinaldi, Stefano
    Divakarachari, Parameshachari Bidare
    Atmakur, Anitha
    ELECTRONICS, 2022, 11 (10)
12345