A survey of FPGA-based accelerators for convolutional neural networks

被引：2
作者：
Sparsh Mittal
机构：
[1] Indian Institute of Technology,Department of Computer Science and Engineering
来源：
Neural Computing and Applications | 2020年 / 32卷
关键词：
Deep learning; Neural network (NN); Convolutional NN (CNN); Binarized NN; Hardware architecture for machine learning; FPGA; Reconfigurable computing; Parallelization; Low power;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Deep convolutional neural networks (CNNs) have recently shown very high accuracy in a wide range of cognitive tasks, and due to this, they have received significant interest from the researchers. Given the high computational demands of CNNs, custom hardware accelerators are vital for boosting their performance. The high energy efficiency, computing capabilities and reconfigurability of FPGA make it a promising platform for hardware acceleration of CNNs. In this paper, we present a survey of techniques for implementing and optimizing CNN algorithms on FPGA. We organize the works in several categories to bring out their similarities and differences. This paper is expected to be useful for researchers in the area of artificial intelligence, hardware architecture and system design.
引用
收藏
页码：1109 / 1139
页数：30
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