A 1.2 V 8-bit 1 MS/s SAR ADC with Res–Cap segment DAC for temperature sensor in LTE

被引:0
作者
H. J. Wu
B. Li
W. C. Huang
Z. P. Li
M. H. Zou
Y. P. Wang
机构
[1] South China University of Technology,School of Electronic and Information Engineering
[2] Guangzhou Rinxin Information and Technology Co.,undefined
[3] Ltd.,undefined
来源
Analog Integrated Circuits and Signal Processing | 2012年 / 73卷
关键词
SAR; ADC; DAC; Switch capacitor; LTE;
D O I
暂无
中图分类号
学科分类号
摘要
A 1.2 V 8-bit single ended successive approximation register analog-to-digital converter (ADC) for long term evolution (LTE) system is implemented. A novel 5-bit resistor and 3-bit capacitor segment digital-to-analog converter is used to minimize the chip area and reduce the product cost. A rail-to-rail amplifier is used as the pre-amplifier of the comparator in order to obtain the full input swing and the adequate gain for low supply. The offset voltage of the comparator is below 2 mV from the Monte Carlo simulated results. The ring oscillator, current generator and bandgap are integrated into the ADC to satisfy multiple applications. The serial peripheral interface is used to adjust the sampling frequency and the key block’s bias current in order to change the dynamic and static power consumption to satisfy the different need in LTE’ modules. The design was fabricated in a 0.13 μm CMOS process with an area of 0.1 mm2 and a power of 1.2 mW. The measurement results show that the differential nonlinearity and integral nonlinearity of the proposed ADC are +0.11/−0.18 LSB and +0.8/−0.04 LSB, respectively. The spurious free dynamic range and signal-to-noise distortion ratio can get 53 and 43.3 dB, respectively.
引用
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页码:225 / 232
页数:7
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[1]  
Xie HL(2011)Single-chip multi-band SAW-less LTE WCDMA and EGPRS CMOS receiver with diversity IEEE Radio Frequency Integrated Circuits Symposium 8 1-4
[2]  
Rakers P(2010)A 900-MHz direct delta-sigma receiver in 65-nm CMOS IEEE Journal of Solid-State Circuits 45 2807-2810
[3]  
Fernandez R(2004)Low pipeline ADC for wireless LANs IEEE Journal of Solid-State Circuits 39 1338-1340
[4]  
McCain T(2011)A 26 μW 8 bit 10 MS/s asynchronous SAR ADC for low energy radios IEEE Journal of Solid-State Circuits 46 1585-1594
[5]  
Xiang J(2008)A 1.8-V 3.1 mW successive approximation ADC in system-on-chip Analog Integrated Circuits and Signal Processing 56 205-211
[6]  
Parkes J(2007)A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC IEEE Journal of Solid-State Circuits 42 2161-2169
[7]  
Riches J(2011)A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS Analog Integrated Circuits and Signal Processing 66 213-221
[8]  
Verellen R(2010)A low power 8 bit successive approximation register A/D for a wireless body sensor node Chinese Journal of Semiconductors 31 065004-5
[9]  
Rahman M(2010)A power-adaptable A/D converter with integrated data compression Analog Integrated Circuits and Signal Processing 64 249-259
[10]  
Shimoni E(2011)An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities Analog Integrated Circuits and Signal Processing 66 389-405