A Multistage Architecture for Statistical Inference with Stochastic Signal Acquisition

被引:0
作者
Corey R.M. [1 ]
Singer A.C. [1 ]
机构
[1] University of Illinois at Urbana-Champaign, Urbana, IL
基金
美国国家科学基金会;
关键词
Parameter estimation; Quantization; Statistical inference; Stochastic circuits;
D O I
10.1007/s11265-015-1020-6
中图分类号
学科分类号
摘要
We describe a statistical inference approach for designing signal acquisition interfaces and inference systems with stochastic devices. A signal is observed by an array of binary comparison sensors, such as highly scaled comparators in an analog-to-digital converter, that exhibit random offsets in their reference levels due to process variations or other uncertainties. These offsets can limit the performance of conventional measurement devices. In our approach, we build redundancy into the sensor array and use statistical estimation techniques to account for uncertainty in the observations and produce a more reliable estimate of the acquired signal. We develop an observational model and find a Cramér-Rao lower bound on the achievable square error performance of such a system. We then propose a two-stage inference architecture that uses a coarse estimate to select a subset of the sensor outputs for further processing, reducing the overall complexity of the system while achieving near-optimal performance. The performance of the architecture is demonstrated using a simulated prototype for parameter estimation and symbol detection applications. The results suggest the feasibility of using unreliable components to build reliable signal acquisition and inference systems. © 2015, Springer Science+Business Media New York.
引用
收藏
页码:425 / 434
页数:9
相关论文
共 11 条
[1]  
Kinget P., Device mismatch and tradeoffs in the design of analog circuits, IEEE Journal Solid-State Circuits, 40, 6, pp. 1212-1224, (2005)
[2]  
Keyes R.W., The effect of randomness in the distribution of impurity atoms on FET thresholds, Applied Physics, 8, 3, pp. 251-259, (1975)
[3]  
Razavi B., Wooley B., Design techniques for high-speed, high-resolution comparators, IEEE Journal Solid-State Circuits, 27, 12, pp. 1916-1926, (1992)
[4]  
Donovan C., Flynn M., A ‘Digital’ 6-bit ADC in 0.25 μm CMOS, IEEE Journal Solid-State Circuits, 37, 3, pp. 432-437, (2002)
[5]  
Paulus C., Bluthgen H.-M., Low M., Sicheneder E., Briils N., Courtois A., Tiebout M., Thewes R., A 4GS/s 6b flash ADC in 0.13 μm CMOS, VLSI Circuits, pp. 420-423, (2004)
[6]  
Sundstrom T., Alvandpour A., Utilizing process variations for reference generation in a flash ADC, IEEE Transactions Circuits System II, Experimentalis Briefs, 56, 5, pp. 364-368, (2009)
[7]  
Weaver S., Hershberg B., Kurahashi P., Knierim D., Moon U.-K., Stochastic Flash Analog-to-Digital Conversion, IEEE Transactions Circuits System II, Experimentalis Briefs, 57, 11, pp. 2825-2833, (2010)
[8]  
Papadopoulos H., Wornell G.W., Oppenheim A., Sequential signal encoding from noisy measurements using quantizers with dynamic bias control, IEEE Transactions Information Theory, 47, 3, pp. 978-1002, (2001)
[9]  
Ribeiro A., Giannakis G., Bandwidth-constrained distributed estimation for wireless sensor networks-Part I: Gaussian case, IEEE Transactions Signal Processing, 54, 3, pp. 1131-1143, (2006)
[10]  
Lehmann E., Casella G., Theory of Point Estimation, (1998)