Real-time FPGA implementation of a secure chaos-based digital crypto-watermarking system in the DWT domain using co-design approach

In this paper a new approach for designing invisible non-blind full crypto-watermarking system targeting images security on FPGA platform is presented. This new design is based on the Hardware-Software co-design approach using the High-Level Synthesis (HLS) tool of Xilinx which allows a good compromise between development time and performances. For a better authentication and robustness of the proposed system, the Discrete Wavelet Transform (DWT) is employed. To more enhance the security level, a new chaos-based generator proposed is integrated into a stream cipher algorithm in order to encrypt and decrypt the watermark during the insertion and extraction phases.This approach allows a better secure access at the positions of the watermark and to distribute the watermark evenly throughout the image. Three novel customized Intellectual Property (IP) cores designed under HLS tool, implementing Haar DWT and the new chaos-based key generator, have been generated, tested, and validated. The generated Register Transfer Level-IP (RTL-IP) cores are integrated into a Vivado library that achieves real-time secured watermarking operations for both embedding and extraction processes. The system has been evaluated using the main metrics in terms of imperceptibility of the produced watermarked images achieving a Peak Signal to Noise Ratio (PSNR) of 47 dB, robustness against most geometric and image processing attacks achieving a Normalized Cross-Correlation (NCC) of 0.99. The proposed crypt-watermarking system allows a good solution against brute force attack which produce a huge key-space of 2768\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2^{768}$$\end{document}. Finally, the implementation offers a good efficiency value of 0.19 MHz/LUT in terms of FPGA resource consumption and speed, making the system a reliable choice for real sensitive embedded applications.