List Scheduling in Embedded Systems Under Memory Constraints

被引:0
|
作者
Paul-Antoine Arras
Didier Fuin
Emmanuel Jeannot
Arthur Stoutchinin
Samuel Thibault
机构
[1] Inria Bordeaux Sud-Ouest,
[2] STMicroelectronics,undefined
[3] University of Bordeaux,undefined
来源
International Journal of Parallel Programming | 2015年 / 43卷
关键词
Task graphs; Scheduling; Memory; System on chip; Video decoding;
D O I
暂无
中图分类号
学科分类号
摘要
Video decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through adequate adjustment of task priorities and judicious resort to insertion-based policy, speedups up to 20 % can be achieved. We also show that our technique allows to prevent deadlock and to substantially reduce the required memory footprint compared to classic list-scheduling heuristics. Lastly, we propose a methodology to assess the appropriateness of dynamic scheduling in this context.
引用
收藏
页码:1103 / 1128
页数:25
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