R-inmac: 10T SRAM based reconfigurable and efficient in-memory advance computation for edge devices

This paper proposes a Reconfigurable In-Memory Advance Computing architecture using a novel 10 SRAM cell. In addition to basic logic operations, the proposed R-InMAC can also implement complex Boolean computing operations such as binary addition/subtraction, binary-to-gray, gray-to-binary conversion, 2’s complement, less/greater than, and increment/decrement. Furthermore, content addressable memory (CAM) operation to search a binary string in a memory array is also proposed efficiently. It can search true and complementary data strings in a single cycle. The proposed R-InMAC architecture’s reconfigurability allows it to be configured according to the needed operation and bit precision, making it ideal and energy-efficient. In addition, compared to the standard SRAM cells, the proposed 10T cell is suited for implementing the XNOR-based binary convolution operation required in Binary Neural Networks (BNNs) with improved latency of 58.89%. The optimized full adder of the proposed R-InMAC shows decrement in the area by 40%, static power by 28%, dynamic power by 55.2%, and latency by 25.3% as compared to conventional designs, making this work a promising candidate for modern edge AI compute in-memory systems.