FPGA implementation of high performance image de-noising filter

This paper presents the high performance based one dimension image filter. Image convolution has been widely used in applications followed by image de-nosing filters, feature extraction and computer vision. Realization of two dimensional(2D) convolution based image filter requires massive computational requirements. FPGA based 2D image filter implementation is one of the most challenging task, more computationally exhaustive due to requirement of large number of multiplications and addition operations. The 2D-filter implementation requires extra memory bandwidth for eliminating Gaussian noise. The proposed one dimension (1D) image filter technique reduces the memory access rate by using pixel reuse. Therefore, it improves the performance as well as flexibility. The novelty of the proposed image de-noising filter is hardware reusability, pixels reuse mechanism in accordance with intermediate data shared for consecutive Multiply and Accumulate (MAC) operations. The optimized Reconfigurable Common Subexpression Elimination (RCSE) based MAC diminishes the area in terms of number of multiplications and adder operations of the filter. The 1D-filter approach uses less number of clock cycles and eliminates the data dependencies among neighborhood pixels. In comparison of state-of the art MAC structures, the proposed latency-hiding MAC design achieves optimal delay of 3.396 ns. An evaluation results show that, the design can achieve 9 times better performance and reduces the 40% of area. The power dissipation of the proposed 1D convolution based image filter architecture is 158mw.