Partitioning and Scheduling DSP Applications with Maximal Memory Access Hiding

被引：0

作者：

Zhong Wang

Edwin Hsing-Mean Sha

Yuke Wang

机构：

[1] University of Notre Dame,Department of Computer Science and Engineering

[2] University of Texas at Dallas,Department of Computer Science

来源：

EURASIP Journal on Advances in Signal Processing | / 2002卷

关键词：

loop pipelining; initial data; maximal overlap; balanced partition scheduling;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

This paper presents an iteration space partitioning scheme to reduce the CPU idle time due to the long memory access latency. We take into consideration both the data accesses of intermediate and initial data. An algorithm is proposed to find the largest overlap for initial data to reduce the entire memory traffic. In order to efficiently hide the memory latency, another algorithm is developed to balance the ALU and memory schedules. The experiments on DSP benchmarks show that the algorithms significantly outperform the known existing methods.

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