Surface Potential and Drain Current 2D Analytical Modeling of Low Power Double Gate Tunnel FET

This submitted work presents the 2-dimensional analytical modeling of Tunnel FET’s in consideration with the inherent properties of dual modulation effect. This effect explains the concept of regulating both gate and also the drain terminal biasing voltage on device surface potential and hence on the tunneling drain current model, which uses the device surface potential modeling as basis of deriving the TFET current model. The model is developed using basic 2-D Poisson’s equation. This analytical model embraces both the biasing voltage effect at gate and drain terminal respectively. The results procured from the submitted work are in perfect agreement with TCAD simulations results and depletion width of various regions defined in TFET is accurate and can also be explained theoretically.