A Highly Area-Efficient Switching Scheme based on Charge Sharing and Capacitor Holding for SAR ADCs

A novel area-efficient capacitor switching scheme for successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. By using the charge-sharing and capacitor-holding technique, the proposed switching method achieves deciding the last three least-significant-bits (LSBs) with only two unit capacitors. Additionally, zero power consumption is achieved in the first conversion cycle, and the monotonic switching method is utilized for the remaining cycles. Compared to the conventional structure, the proposed switching scheme reduces the average switching energy by 97.71% and achieves an 87.5% capacitor area reduction without an extra reference voltage or capacitor-splitting structure. A postlayout simulation of a 1-V 10-bit 5-MS/s SAR ADC in 180 nm CMOS technology is performed, which verifies the feasibility of the proposed switching scheme. The SAR ADC achieves a 58.9 dB signal-to-noise and distortion ratio (SNDR) and 72.1 dB spurious-free dynamic range (SFDR).