共 43 条
- [1] Taur Y(1997)CMOS scaling into nanometer regime Proc. IEEE 85 486-504
- [2] Kim K(2001)Double-gate CMOS: symmetrical-versus asymmetrical-gate devices IEEE Trans. Electron Devices 48 294-299
- [3] Fossum JG(1975)The effect of randomness in the distribution of impurity atoms on FET threshold Appl. Phys. A 8 251-259
- [4] Keyes RW(1994)Ultrafast operation of Vth-adjusted p+-n+ double gate SOI MOSFETs IEEE Electron Device Lett. 15 386-388
- [5] Tanaka T(2003)Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching IEEE Electron Device Lett. 24 484-486
- [6] Suzuki K(2000)Finfet-a self aligned double-gate MOSFET scalable to 20 nm IEEE Trans Electron Devices 47 2320-2325
- [7] Horie H(2012)Ground plane fin-shaped field effect transistor (GP-FinFET): a FinFET for low leakage power circuits Microelectron. Eng. 95 74-82
- [8] Sugii T(2012)G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems IEICE Electron. Express 9 881-887
- [9] Liu Y(2001)Short-channel vertical sidewall MOSFETs IEEE Trans. Electron Devices 48 1783-1788
- [10] Hisamoto Digh(2002)Top contacts for vertical double-gate MOSFETs Microelectron. Eng. 64 465-471