Dead zone-less low power phase frequency detector, independent of duty cycle variations for charge pump phase locked loop

被引:0
作者
Marichamy Divya
Kumaravel Sundaram
机构
[1] Vellore Institute of Technology,Department of Micro and Nano Electronics, School of Electronics Engineering
来源
Analog Integrated Circuits and Signal Processing | 2023年 / 114卷
关键词
Phase frequency detector; Phase difference; Dead zone; Linearity;
D O I
暂无
中图分类号
学科分类号
摘要
In phase frequency detector (PFD) phase characteristics, the presence of dead zone fails to turn on the charge pump (CP) of the phase locked loop (PLL). This degrades the phase noise in PLL. To overcome this drawback in PFD, a circuit to eliminate dead zone using pass transistor logic (PTL) and delay cells (DCs) is proposed in this paper. The proposed circuit has been implemented in UMC 0.18 μm\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu \mathrm{m}$$\end{document} CMOS process and simulated in a cadence spectre environment. From the post layout simulation results, it is noted that for a phase difference of -π\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$- \pi$$\end{document} to +π\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$+ \pi$$\end{document}, the PFD achieves 100% linearity and is free from the dead zone. The designed PFD consumes power of 28.8 μ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu$$\end{document}W at an operating frequency of 100 MHz. The proposed PFD is also verified across process voltage temperature (PVT) variations for its linearity. The PFD is independent of duty cycle variations of its input clock signals. It occupies an area of 312.4 μm2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu \mathrm{m}^{2}$$\end{document}.
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页码:13 / 30
页数:17
相关论文
共 36 条
[1]  
Koithyar A(2018)A faster phase frequency detector using transmission gate-based latch for the reduced response time of the PLL International Journal of Circuit Theory and Applications 46 842-854
[2]  
Ramesh T(2015)Investigating phase detectors: Advances in mature and emerging phase-frequency and time-to-digital detectors in phase-locked looped systems IEEE Microwave Magazine 16 56-78
[3]  
Minhad KN(2020)A high-speed, power efficient, dead-zone-less phase frequency detector with differential structure Microelectronics Journal 97 1750179-299
[4]  
Reaz MBI(2017)Precharged phase detector with zero dead-zone and minimal blind-zone Journal of Circuits, Systems and Computers 26 295-3263
[5]  
Ali SHM(1998)A simple precharged CMOS phase frequency detector IEEE Journal of Solid-State Circuits 33 3253-389
[6]  
Abolhasani A(2009)A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by IEEE Journal of Solid-State Circuits 44 377-940
[7]  
Mousazadeh M(2021)Low-power high-speed phase frequency detector based on carbon nano-tube field effect transistors Analog Integrated Circuits and Signal Processing 108 936-91
[8]  
Khoei A(2021)PFD with improved average gain and minimal blind zone combined with lock-in detection for fast settling PLLs Microelectronics Journal 116 83-3563
[9]  
Nikolić G(2010)Phase frequency detector with minimal blind zone for fast frequency acquisition IEEE Transactions on Circuits and Systems II: Express Briefs 57 3549-1552
[10]  
Jovanović G(2018)A novel zero dead zone PFD and efficient CP for PLL applications Analog Integrated Circuits and Signal Processing 95 1542-539