Realization of high-speed logic functions using heterojunction vertical TFET

In this paper, a dual-gate silicon–germanium heterojunction vertical TFET with germanium as the source material (HJ-VTFET) is proposed for realizing compact logic functions. A single device with both gate terminals is biased independently during 2D simulation to understand fundamental two-input Boolean gates (OR, NAND, AND and NOR). The vital element in attaining various logic functions using double-gate vertical TFET is deploying a gate–source connection with an appropriate choice of silicon body thickness. The OR and NAND gates are realized using n-type and p-type HJ-VTFETs, respectively, by applying an independent voltage at both gates. While the AND and NOR gates are realized using n-type and p-type HJ-VTFETs, respectively, employing the gate–source overlap method. These implementations show that an exclusive feature of TFETs, such as ambipolar conduction with tunneling dependent on gate–source overlapping, can be realized for logic functions. With such a compact implementation with HJ-VTFET, the present work revealed some serious problems, such as a large subthreshold swing (SS), a small ON-state current (ION\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$I_\textrm{ON}$$\end{document}), and high propagation delay (τD\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\tau _\textrm{D}$$\end{document}). For AND functionality, in contrast to pure Si-based-VTFET (Si-VTFET), the HJ-VTFET raised ION\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$I_\textrm{ON}$$\end{document}/IOFF\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$I_\textrm{OFF}$$\end{document} via 3rd-order magnitude with around 67% improvement in SS. Further, an OR gate is realized with proposed HJ-VTFET and revealed less τD\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\tau _\textrm{D}$$\end{document} around 0.012 nS, compared to the other gates realized using HJ-VTFET.