CNFET-based digitally controlled impedance multiplier

被引:0
|
作者
Tripathi S.K. [1 ]
Tiwari U. [1 ]
机构
[1] Department of Electrical Electronics and Communication Engineering, Sharda University India, Greater Noida
关键词
Carbon nanotube field effect transistor (CNFET); CMOS; Digital control; Impedance multiplier;
D O I
10.1007/s41870-021-00757-0
中图分类号
学科分类号
摘要
In this paper, a carbon nanotube-FET based impedance multiplier is presented. The circuit uses digitally controlled inverting current conveyor (DCICC). Proposed circuit is functioning accurately with a multiplication factor from 0 to 7. The technique is simple, versatile and compatible for microelectronics. The proposed circuit uses only one active element along with a grounded capacitor. The tuning of impedance is based on the number of tubes in a CNFET with switched on condition which is selected by a digital control technique. The circuit operates with low supply voltage of 0.7 V. The results of DCICC have been verified through HSPICE simulation. © 2021, Bharati Vidyapeeth's Institute of Computer Applications and Management.
引用
收藏
页码:1937 / 1941
页数:4
相关论文
共 50 条
  • [1] CNFET-Based Energy-Efficient 4:2 Compressor for Multiplier Applications
    Hussain, Inamul
    Chaudhury, Saurabh
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2025, 34 (03)
  • [2] Defect Tolerance for CNFET-based SRAMs
    Li, Tianjian
    Jiang, Li
    Liang, Xiaoyao
    Xu, Qiang
    Chakrabarty, Krishnendu
    PROCEEDINGS 2016 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2016,
  • [3] On Microarchitectural Modeling for CNFET-based Circuits
    Li, Tianjian
    Chen, Hao
    Qian, Weikang
    Liang, Xiaoyao
    Jiang, Li
    2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2015, : 356 - 361
  • [4] CNFET-Based High Throughput SIMD Architecture
    Jiang, Li
    Li, Tianjian
    Jing, Naifeng
    Kim, Nam Sung
    Guo, Minyi
    Liang, Xiaoyao
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (07) : 1331 - 1344
  • [5] Optimal Redundancy Designs for CNFET-Based Circuits
    Cheng, Da
    Wang, Fangzhou
    Gao, Feng
    Gupta, Sandeep K.
    2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS), 2014, : 25 - 32
  • [6] Performance Evaluation of CNFET-Based Logic Gates
    Cho, Geunho
    Kim, Yong-Bin
    Lombardi, Fabrizio
    Choi, MinSu
    I2MTC: 2009 IEEE INSTRUMENTATION & MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1-3, 2009, : 882 - +
  • [7] Logical Effort model for CNFET-based circuits
    Ali, Muhammad
    Ahmed, Mohammad
    Chrzanowska-Jeske, Malgorzata
    2014 IEEE 14TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2014, : 460 - 465
  • [8] Design and Evaluation of CNFET-Based Quaternary Circuits
    Moaiyeri, Mohammad Hossein
    Navi, Keivan
    Hashemipour, Omid
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2012, 31 (05) : 1631 - 1652
  • [9] Design and Evaluation of CNFET-Based Quaternary Circuits
    Mohammad Hossein Moaiyeri
    Keivan Navi
    Omid Hashemipour
    Circuits, Systems, and Signal Processing, 2012, 31 : 1631 - 1652
  • [10] CNFET-Based Ternary Inverter and its Variability Analysis
    Anand, Arpit
    Islam, Aminul
    2014 3RD INTERNATIONAL CONFERENCE ON RELIABILITY, INFOCOM TECHNOLOGIES AND OPTIMIZATION (ICRITO) (TRENDS AND FUTURE DIRECTIONS), 2014,