共 50 条
- [2] SHORT SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS UNDER ARBITRARY FAULTS OF GATES PRIKLADNAYA DISKRETNAYA MATEMATIKA, 2022, (55): : 59 - 76
- [3] Fault-tolerant multiple bus networks for fan-in algorithms 10TH INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM - PROCEEDINGS OF IPPS '96, 1996, : 674 - 681
- [4] ON LOGIC NETWORKS ALLOWING SHORT SINGLE FAULT DETECTION TESTS UNDER ARBITRARY FAULTS OF GATES PRIKLADNAYA DISKRETNAYA MATEMATIKA, 2021, (51): : 85 - 100
- [6] LOGIC DESIGN AUTOMATION OF MOS COMBINATIONAL NETWORKS WITH FAN-IN, FAN-OUT CONSTRAINTS. 1978, : 240 - 249
- [9] Fault detection and diagnostic tests for logic gates DISCRETE MATHEMATICS AND APPLICATIONS, 2014, 24 (04): : 213 - 225
- [10] FINDING COMPLETE FAULT-DETECTION TESTS FOR COMBINATIONAL LOGIC NETS BY THE MAXIMUM EQUIVALENT FORM COVERING METHOD AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1979, (04): : 33 - 38