A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC

被引:0
作者
Amir Arian
Mehdi Saberi
Saied Hosseini-Khayat
Reza Lotfi
Yusuf Leblebici
机构
[1] Ferdowsi University of Mashhad,
[2] Swiss Federal Institute of Technology (EPFL),undefined
来源
Analog Integrated Circuits and Signal Processing | 2012年 / 71卷
关键词
Digital-to-analog converter; Redundant successive approximation ADC; Redundant search algorithm; Split capacitive-array DAC; High speed SAR ADC;
D O I
暂无
中图分类号
学科分类号
摘要
A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 μm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.
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页码:583 / 589
页数:6
相关论文
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