Restart Optimization for Transactional Memory with Lazy Conflict Detection

被引:0
作者
Miloš Cvetanović
Zaharije Radivojević
Veljko Milutinović
机构
[1] University of Belgrade,School of Electrical Engineering
来源
International Journal of Parallel Programming | 2017年 / 45卷
关键词
Transactional memory; Restart optimization; Analytical modeling; Continuous-time modeling; Performance analysis;
D O I
暂无
中图分类号
学科分类号
摘要
This paper presents an optimization algorithm for transactional memory with lazy conflict detection. The proposed optimization attempts to minimize the execution time of restarted transactions. Minimizing happens during restart, by avoiding the re-execution of a section of a transaction that is unaffected by the restart. The proposed optimization builds on previous research and differs in that it eliminates the need for the prediction of conflicting accesses and introduces incremental context saving. Moreover, the paper introduces analytical models for estimating the execution time of transactions, with and without the restart optimization, that are developed using the continuous-time model. A critical evaluation comparing analytical models with the simulation results is discussed in the paper.
引用
收藏
页码:482 / 507
页数:25
相关论文
共 58 条
[1]  
McDonald A(2007)Transactional memory: the hardware–software interface IEEE Micro 27 67-76
[2]  
Carlstrom BD(2007)Transactional memory: an overview IEEE Micro 27 8-29
[3]  
Chung J(2006)Unbounded transactional memory IEEE Micro 26 59-69
[4]  
Minh CC(2010)Lightweight transactional memory systems for NoCs based architectures: design, implementation and comparison of two policies J. Parallel Distrib. Comput. 70 1024-1041
[5]  
Chafi H(2008)Performance pathologies in hardware transactional memory IEEE Micro 28 32-41
[6]  
Kozyrakis C(2011)Hybrid transactional memory with pessimistic concurrency control Int. J. Parallel Prog. 39 375-396
[7]  
Olukotun K(2004)Transactional coherence and consistency: simplifying parallel hardware and software IEEE Micro 24 92-103
[8]  
Harris T(2014)Removal of conflicts in hardware transactional memory systems Int. J. Parallel Prog. 42 198-218
[9]  
Cristal A(2013)Hardware signature designs to deal with asymmetry in transactional data sets IEEE Trans. Parallel Distrib. Syst. 24 506-519
[10]  
Unsal OS(2010)A direct coherence protocol for many-core chip multiprocessors IEEE Trans. Parallel Distrib. Syst. 21 1779-1792