An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

被引：0
|
作者：
Yung-Chi Chang
Chao-Chih Huang
Wei-Min Chao
Liang-Gee Chen
机构：
[1] National Taiwan University,DSP/IC Design Lab., Department of Electrical Engineering and Graduate Institute of Electronics Engineering
来源：
Journal of VLSI signal processing systems for signal, image and video technology | 2005年 / 41卷
关键词：
MPEG-4; video decoding; bitstream parsing processor; data partitioned bitstream parsing;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.
引用
收藏
页码：183 / 191
页数：8
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