A mathematical steady-state design model for fully-integrated boost and buck DC–DC converters

被引：0
|
作者：
Mike Wens
Michiel Steyaert
机构：
[1] Katholieke Universiteit Leuven,
来源：
Analog Integrated Circuits and Signal Processing | 2012年 / 70卷
关键词：
DC–DC; Model; Step-down; Step-up; Integrated output filter;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This brief discusses a mathematical steady-state model for fully-integrated boost and buck DC–DC converters, which takes all the significant resistive and dynamic power losses into account. The model provides a reduced calculation time by a factor 30 compared to SPICE. A 2%, or less, deviation in comparison with SPICE is achieved. The validation of the model through the measurements of both a fully-integrated boost and buck converter is demonstrated, resulting in an accuracy for the efficiency of 3 and 4% respectively.
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页码：369 / 375
页数：6
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