Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism

Although several synthesis methods for asynchronous circuits exist, only limited test methodologies have been developed. This paper presents a built-in self-test (BIST) architecture for Multi-Threshold NULL Convention Logic (MTNCL) asynchronous circuits that utilizes an automated, industry-standard tool-based flow. The software procedure for, and hardware components to implement, BIST functionality are explained. To improve testing performance, the MTNCL pipeline is separated into multiple parallel BIST circuits, with standard pipeline components doubling as BIST circuitry to reduce area overhead. Results of this BIST architecture and software performance is explored for three different test cases looking at area impact and effects of varying the number of input patterns and initial seeds. Further refinements to fault exclusions based upon operating principles of MTNCL are developed to better depict actual fault coverage; and additional hardware modifications are proposed to improve controllability and observability to further increase fault coverage.