A 2.8–10-GHz CMOS Current Reuse Cascaded Linearity Improving Ultra-Wideband Low-Noise Amplifier

This study presents a wideband low-noise amplifier (LNA) chip that covers the frequency range of 2.8–10 GHz using UMC’s 0.18 μm complementary metal–oxide–semiconductor technology. The LNA adopts a current reuse architecture to reduce power consumption. This study improves linearity using multiple gated transistors and inductance degeneration techniques. In addition to enhancing linearity, the proposed technique also achieves high gain and broadband. The DC power dissipation of this LNA was 18 mW with a 1.5 V supply voltage. The measured minimum noise figure was 4.5 dB. Furthermore, the gain, input third-order intercept point, and total chip size of the LNA were 10.8–13.8 dB, 2 dBm, and 1.18 × 1.19 mm2, respectively. The proposed LNA measurements exhibit high linearity, high gain, an optimal reflection coefficient, and a low supply voltage.