Analog Building Blocks Using QFGMOS Technique

被引：0
作者：
Rishikesh Pandey
Bhanu Kiran
机构：
[1] Thapar Institute of Engineering and Technology (Deemed to be University),
来源：
Wireless Personal Communications | 2020年 / 111卷
关键词：
Analog circuits; Circuit simulation; CMOS technology; Current divider; Function generator; Harmonic distortion;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
In this paper, quasi-floating gate MOSFET (QFGMOS) based current divider and pseudo-exponential function generator circuits are proposed. The use of QFGMOS makes the proposed circuits suitable for low voltage/low power operation. The proposed circuits have lower power supply voltage requirement, lower power dissipation and lower THD than the existing circuits available in literature. Both the circuits have been designed and simulated in Cadence virtuoso analog design environment using 180 nm CMOS technology. The simulation results have also been presented to validate the performance of the proposed circuits.
引用
收藏
页码：1019 / 1031
页数：12
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