A two-stage CMOS OTA with enhanced transconductance and DC-gain

An ultra-low-power process-insensitive two-stage OTA working in weak inversion region with enhanced transconductance and DC gain is presented in this paper. The proposed two-stage OTA is based on a bulk-driven input stage with rail-to-rail input voltage range, in which the bulk transconductance is enhanced by means of a partial positive-feedback loop. At the same time, a pseudo-cascode frequency compensation technique is applied in this design to improve the phase margin and accordingly, robust the stability of the proposed OTA. In addition, the proposed composite-transistor structure is used to improve output impedance of the two-stage OTA in weak inversion region. As a result, the improvement of DC gain and gain-bandwidth is obtained. Transistor-level simulations and results in UMC 0.18 μm\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu \hbox {m}$$\end{document} CMOS process confirm the theoretical results. Simulated from a 0.5 V supply voltage, the proposed two-stage OTA achieves a 111.5 dB DC gain, a gain-bandwidth product of 9.5 kHz and a phase-margin of 66∘\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$66^{\circ }$$\end{document} while driving a 15 pF load.