As the technology feature size shrinks, leakage power is dominating in the total chip power consumption of VLSI circuits. In this work to reduce the leakage power, sleepy transistor technique is used for differential ring oscillator (RO). First design is proposed using CMOS inverter stage in a differential manner to form ring oscillator with sleepy NMOS and sleepy PMOS transistors. Second design of differential ring oscillator is proposed with CMOS cross-coupled cell with sleepy NMOS and PMOS transistors. Further, substrate-biasing concept has been applied to proposed design for improvement in the power consumption. The power consumption for sleepy NMOS inverter stage differential ring oscillator (RO) is 0.696–0.953 mW and the frequency of operation is 3.09–4.56 GHz. Sleepy NMOS cross-coupled based ring oscillator design shows the power consumption of 0.78–1.21 mW at an operating frequency of 2.23–4.25 GHz. The power consumption for sleepy PMOS inverter stage differential RO design is 1.95–2.04 mW and the frequency of operation is 4.41–4.63 GHz. Further, sleepy PMOS cross-coupled RO design shows power consumption of 0.97–1.06 mW at an operating frequency of 2.26–2.41 GHz. The substrate biasing of sleepy NMOS inverter stage ring oscillator design gives power consumption of 0.862–0.924 mW and the frequency of operation is 4.16–4.45 GHz. Substrate biasing of sleepy NMOS cross-coupled ring oscillator design shows power consumption of 1.06–1.16 mW and output frequency varies from 1.86–2.05 GHz. The simulations have been performed using SPICE in 0.18 µm CMOS technology. Results of power consumption, tuning range, phase noise, FoM and output frequency have been compared with earlier circuits and proposed circuits show improvement in results.
