A Linear CMOS Voltage-to-Current Converter

An improved complementary metal oxide semiconductor (CMOS) voltage-to-current converter is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting of the proposed converter to avoid the body effect. To accurately annihilate the nonlinear voltage terms, a better modeling of the drain-to-source current of the MOS transistor operating in the linear region is essential and is adopted. Specifically, the substrate-bias effect of the MOS transistor is treated more accurately in our design. Consequently, the nonlinearity of the large-signal transconductance of the converter is reduced. The voltage-to-current converter is designed and fabricated in a 0.35 μm CMOS technology. The fabricated circuit occupies an area of 267 μm × 197 μm (≈0.053 mm2) and dissipates 3.92 mW from a 3.3 V supply. The measured and simulated data are in good agreement. For a 1 VP-P input voltage, the measured total harmonic distortion (THD) of the output current is less than 1.2%.