Performance Evaluation of Wordlength Reduction Based Area and Power Efficient Approximate Multiplier for Mobile Multimedia Applications

Hardware multiplier circuits decide the speed and power consumption in the execution of digital signal processing algorithms. The desirable feature of reduced area and power consumption for battery-driven multimedia gadgets can be realized by replacing the power hungry multiplier circuits with approximate multiplier circuits. The approximation techniques reduce the complexity of the design and improve the energy efficiency of the circuit. This paper proposes an area and power efficient approximate unsigned integer multiplier architecture based on wordlength reduction. It is designed to meet a pre-specified error performance with improved area and power reduction compared with similar designs. It is extended further for the signed multiplier architecture. The circuit characteristics are analyzed to establish the suitability of the proposed design for low-power applications. Synthesis results show that the proposed unsigned multiplier consumes 65% less power than the exact Wallace multiplier. The area requirement of the proposed multiplier reduces by 50% compared to an exact multiplier. The multiplier is tested for image filtering to establish the efficacy of the design in multimedia applications.