A New High-Speed, Low-Area Residue-to-Binary Converter For the Moduli Set {24n,22n+1,2n+1,2n-1}\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\{ 2^{4n} ,2^{2n} + 1,2^{n} + 1,2^{n} - 1\}$$\end{document} Based on CRT-1

The implementation of reverse converter is one of the most important elements influencing the performance of a residue number system. In this research, we propose an efficient high-speed and low-area reverse converter for moduli set {24n,22n+1,2n+1,2n-1}\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\{ 2^{4n} ,2^{2n} + 1,2^{n} + 1,2^{n} - 1\}$$\end{document}. Due to the form of the moduli set, we have implemented the proposed reverse converter using Chinese remainder theorem and dynamic range division technique, which have resulted in a simpler design, lower area consumption and higher conversion speed compared to previous studies. To have a fair comparison between the proposed reverse converter and the recently presented converters with similar moduli sets, we used Xilinx ISE 13.1 FPGA simulator to derive area and delay, which are measured to cover the various dynamic ranges up to 256 bit. The experimental results show that the proposed reverse converter achieves an average 20% area time saving compared to the recently presented converters for similar moduli set.