A hybrid crossbar-ring on chip network topology for performance improvement of multicore architectures

Multicore architectures have achieved a popularity to deliver improved performance for different application domains. Performance of a system is depending on various factors like instruction set architecture, compiler, types of cores, memory technologies, on chip interconnect topology. The role of computer architect is to propose an application specific design that improves performance of the architecture through different techniques. There are different performance parameters that affects performance of multicore architectures. The most common valued parameters include execution time and energy consumption. All classes of multicore architectures still attempt to provide more energy aware solutions in it. This work proposes a hybrid crossbar-ring on chip network topology. This topology is a hybrid topology that uses a crossbar switch or router and a ring. It divides the network in number of segments. The application environment with more intrasegment communication utilizes this solution in efficient manner as less number nodes are involved in a segment. The focus of the work is to improve the performance in terms of average hop count, packet latency, execution time and energy. The packet latency is improved keeping average hope count constant. The execution time is decreased on average by 6.26% with a maximum decrease by 8.84%. The total energy consumption is reduced by 5.93% on average. The proposed hybrid crossbar-ring on chip network topology outperforms the segmented bus topology by keeping the average hop count in a fixed range. © 2023, The Author(s), under exclusive licence to Bharati Vidyapeeth's Institute of Computer Applications and Management.