Clock glitch fault injection attack on an FPGA-based non-autonomous chaotic oscillator

被引:0
作者
Talal Bonny
Qassim Nasir
机构
[1] University of Sharjah,Department of Electrical and Computer Engineering
来源
Nonlinear Dynamics | 2019年 / 96卷
关键词
Non-autonomous chaotic oscillators; Clock glitch; NIST; FPGA;
D O I
暂无
中图分类号
学科分类号
摘要
Chaos-based true random bit generators have been demonstrated in many studies to be feasible and secure for crypto-system applications. In this work, we demonstrate that an FPGA-based non-autonomous chaotic oscillator, used as a true random number generator, can be compromised via cryptanalysis attacks. First, we realize non-autonomous chaotic oscillator (previously implemented only in analog form) on a modular FPGA platform. The oscillator architecture is simplified to eliminate the Sin function and is described in details in VHDL. Then, we propose chaotic oscillator attacking system including clock glitch generator to compromise the oscillator by injecting glitches on function clock. The parameters and positions of those glitches are carefully determined to achieve a successful attack. The experimental results show that the system is attacked, and the generated glitched bit-streams are distorted, unlike the bit-streams generated without glitching. The randomness of the generated bit-streams is checked using the NIST test tool.
引用
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页码:2087 / 2101
页数:14
相关论文
共 88 条
[1]  
Saleh S(2013)A secure data communication system using cryptography and steganography Int. J. Comput. Netw. Commun. (IJCNC) 5 125-137
[2]  
Filali RL(2014)Observer-based secure communication design using discrete-time hyperchaotic systems Commun. Nonlinear Sci. Numer. Simul. 19 1424-1432
[3]  
Benrejeb M(2007)Truly random number generators based on a non-autonomous chaotic oscillator Int. J. Electron. Commun. 61 235-242
[4]  
Borne P(2017)Dynamical response of electrical activities in digital neuron circuit driven by autapse Int. J. Bifurc. Chaos 27 1750187-24288
[5]  
Ergun S(2019)Hardware optimized FPGA implementations of high speed true random bit generators based on switching-type chaotic oscillators J. Circuits Syst. Signal Process. 38 1342-5122
[6]  
O zoguz S(2018)Chaos and multi-scroll attractors in RCL-shunted junction coupled Jerk circuit connected by memristor PLoS ONE 13 e0191120-59
[7]  
Ren G(2018)Topological horseshoe analysis, ultimate boundary estimations of a new 4D hyperchaotic system and its FPGA implementation Int. J. Bifurc. Chaos 28 1850081-102
[8]  
Zhou P(2018)Image edge detectors under different noise levels with FPGA implementations J. Circuits Syst. Comput. 27 1850209-1750055
[9]  
Ma J(2018)Multiple histogram-based face recognition with high-speed FPGA implementation J. Multimed. Tools Appl. 77 24269-833
[10]  
Cai N(2013)A survey on the integrated design of chaotic oscillators Appl. Math. Comput. 219 5113-6263