A 24-GHz power amplifier with Psat of 15.9 dBm and PAE of 14.6 % using standard 0.18 μm CMOS technology

被引：0
作者：
Yo-Sheng Lin
Jing-Ning Chang
机构：
[1] National Chi Nan University,Department of Electrical Engineering
来源：
Analog Integrated Circuits and Signal Processing | 2014年 / 79卷
关键词：
CMOS; 24 GHz; Power amplifier; Saturated output power; Power added efficiency;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
A 24 GHz power amplifier for direct-conversion transceiver using standard 0.18 μm CMOS technology is reported. The three-stage power amplifier comprises two cascaded cascode stages for high power gain, followed by a common-source stage for high power linearity. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a Wilkinson-power-divider- and combiner-based two-way power dividing and combining architecture. The power amplifier consumes 163.8 mW and achieves power gain (S21) of 22.8 dB at 24 GHz. The corresponding 3-dB bandwidth of S21 is 4.2 GHz, from 22.7 to 26.9 GHz. At 24 GHz, the power amplifier achieves Psat of 15.9 dBm and maximum PAE of 14.6 %, an excellent result for a 24 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP1dB) is 7 dBm at 24 GHz. These results demonstrate the proposed power amplifier architecture is very promising for 24 GHz short-range communication system applications.
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页码：427 / 435
页数：8
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