A Comprehensive Analysis of Different SRAM Cell Topologies in 7-nm FinFET Technology

Complementary metal-oxide-semiconductor (CMOS) device faces various unknown short channel effects (SCEs) such as subthreshold leakage and drain-induced barrier lowering (DIBL) in advanced technologies. This degrades the circuit’s performance, especially SRAM cell, owing to the high demand for large density. Fin-shaped field-effect transistor (FinFET) is one of the trending choices for memory designers, which can improve the stability and minimize the SCEs of the CMOS devices. In this study, different SRAM cell topologies are redesigned and re-simulated by using 7-nm FinFET devices, and then, their performance metrics including the stability, access time, and power are measured at a certain range of supply voltage (VDD) below the nominal value of 0.7 V. Moreover, the layout of these SRAM cells is designed and compared in which the ST12T cell consumes the maximum area due to having a higher count of transistors. Simulated results inferred that the ST11T cell offers the highest RSNM among all the SRAM cells, which can be explained with the use of read decoupling technique and cross-coupled Schmitt-trigger inverters. Moreover, the ST12T cell has the highest WSNM in comparison to other SRAM cells because this cell performs its write operation in fully differential form along with a power-gating write-assist technique. In the view of power consumption, the ST11T and ST12T cell offers the least dynamic and leakage power dissipation, respectively, because the former cell is single-ended bitcell with a low frequency and the latter one has stacked transistors in its cell core in which the path from power VDD to GND is long. An electrical quality metric (EQM) is utilized to assess the overall performance of these SRAM cells, which displays the superiority of the ST12T cell.