Genetic Algorithm for Boolean minimization in an FPGA cluster

被引：0
|
作者：
César Pedraza
Javier Castillo
José I. Martínez
Pablo Huerta
Jose L. Bosque
Javier Cano
机构：
[1] Universidad Rey Juan Carlos,DATCCCIA, ETSII
[2] Universidad de Cantabria,Facultad de Ciencias, Dpto. de Electrónica y Computadores
来源：
The Journal of Supercomputing | 2011年 / 58卷
关键词：
Performance evaluation; FPGA; Boolean synthesis; Hardware co-design;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Evolutionary algorithms are an alternative option to the Boolean synthesis due to that they allow one to create hardware structures that would not be able to be obtained with other techniques. This paper shows a parallel genetic programming (PGP) Boolean synthesis implementation based on a cluster of FPGAs that takes full advantage of parallel programming and hardware/software co-design techniques. The performance of our cluster of FPGAs implementation has been compared with an HPC implementation. The experimental results have shown an excellent behavior in terms of speed up (up to ×500) and in terms of solving the scalability problems of this algorithms present in previous works.
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页码：244 / 252
页数：8
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