Clock delay-based design for hysteresis programming and noise reduction in dynamic comparators

Schmitt Triggers have found wide spread use in low-power and threshold-based applications such as peak detectors and spectrum analyzers. They are formed by comparators and feedback loops and exhibit hysteresis at nominal supply voltage. When using dynamic comparators, the periodic discharge of internal capacitors prior to each decision process cancels hysteresis. In addition, dynamic comparators produce considerable noise that may affect the operation of hysteresis-based applications. Therefore, currently, Schmitt Triggers are mainly designed as static circuits at the price of less operation speed, more silicon area and higher power consumption compared to their analog counterparts. This paper presents a new low-noise dynamic comparator with programmable hysteresis. Using an advanced comparator structure, as the two-stage dual-clock latch comparator, the hysteresis could be adjusted over more than 30 mV by programming the delay between the two clocks. Moreover, the same delay has been used to reduce the switching noise. The peak kickback noise is then reduced by more than 70%. This has been achieved by designing a customized 4-bit programmable delay circuit. Although several functionalities have been added to the circuit, the proposed design include only a few extra elements with respect to the basic one. As a result, the total consumed energy at 500 MHz is 1.2 pJ/decision only, while the static power consumption is less than 65 pW.