A Step Toward Real-Time Time–Frequency Analyses with Varying Time–Frequency Resolutions: Hardware Implementation of an Adaptive S-transform

This paper addresses the rarely considered issue of hardware implementation of the S-transform, a very important time–frequency representation with many practical applications. Various improved, adaptive, and signal-driven versions of the S-transform have been developed over the years, but only its basic (non-adaptive) form has been implemented in hardware. Here, a novel hardware implementation of the adaptive S-transform is proposed extending the previously developed design. To minimize hardware demands, the proposed approach is based on an appropriate approximation of the frequency window function considered in the S-transform. The adaptivity of the transform to the signal is achieved by an optimal choice of a window parameter from the set of predefined values, meaning that for each window parameter the S-transform is calculated. To additionally save hardware resources, the proposed design does not require storing all calculated values, but only two in each iteration. The proposed multiple-clock-cycle architecture is developed on the field-programmable gate array device, and its performance is compared with other possible implementation approaches such as the hybrid and single-clock-cycle ones. It is demonstrated that the developed design minimizes hardware complexity and clock cycle time compared to alternative approaches and is significantly more efficient than the software realization. Both noiseless and noisy multicomponent highly nonstationary signals were considered. An excellent match between the results of the hardware and the “exact” adaptive S-transform evaluation obtained through the MATLAB implementation is demonstrated. Lastly, the execution time that can be estimated in advance is also an important practical feature of the developed design.