共 50 条
- [1] Estimation of BIST resources during high-level synthesis JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1998, 13 (03): : 221 - 237
- [2] Lower bound estimation of hardware resources for scheduling in high-level synthesis Journal of Computer Science and Technology, 2002, 17 : 718 - 730
- [4] Estimation and consideration of interconnection delays during high-level synthesis 24TH EUROMICRO CONFERENCE - PROCEEDING, VOLS 1 AND 2, 1998, : 349 - 356
- [5] Controller estimation for FPGA target architectures during high-level synthesis ISSS'02: 15TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS, 2002, : 56 - 61
- [7] Testability improvement during high-level synthesis ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2003, : 505 - 505
- [8] Power Estimation Methodology for a High-Level Synthesis Framework ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, : 541 - +
- [9] A constructive method for data path area estimation during high-level VLSI synthesis PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997, 1996, : 509 - 515