A Multiple-Valued Logic for Implementing a Random Oracle and the Position-Based Cryptography

被引:0
|
作者
Alexey Yu. Bykovsky
机构
[1] Lebedev Physical Institute,
[2] Russian Academy of Sciences,undefined
来源
Journal of Russian Laser Research | 2019年 / 40卷
关键词
position-based cryptography; quantum network; random oracle; hash function; multiplevalued logic;
D O I
暂无
中图分类号
学科分类号
摘要
From the theoretical point of view, the quantum network in conjunction with a random oracle can provide a higher level of security for the position-based cryptography. The practical implementation of such schemes is quite possible and can be based on a multiple-valued logic function with random parameters.
引用
收藏
页码:173 / 183
页数:10
相关论文
共 50 条
  • [31] AN EFFECTIVE IMMUNE ALGORITHM FOR MULTIPLE-VALUED LOGIC MINIMIZATION PROBLEMS
    Gao, Shangce
    Tang, Zheng
    Vairappan, Catherine
    INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL, 2009, 5 (11A): : 3961 - 3969
  • [32] Voltage-mode multiple-valued logic adder circuits
    Thoidis, IM
    Soudris, D
    Thanailakis, A
    IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (06): : 1054 - 1061
  • [33] Mathematical foundation on static hazards in multiple-valued logic circuits
    Takagi, N
    Nakashima, K
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2003, E86A (06): : 1525 - 1534
  • [34] A multiple-valued logic approach to the design and verification of hardware circuits
    Rosenmann, Amnon
    JOURNAL OF APPLIED LOGIC, 2016, 15 : 69 - 93
  • [35] A learning multiple-valued logic network: Algebra, algorithm, and applications
    Tang, Z
    Cao, QP
    Ishizuka, O
    IEEE TRANSACTIONS ON COMPUTERS, 1998, 47 (02) : 247 - 251
  • [36] Implementation of a DRAM-cell-based multiple-valued logic-in-memory circuit
    Kimura, H
    Hanyu, T
    Kameyama, M
    IEICE TRANSACTIONS ON ELECTRONICS, 2002, E85C (10): : 1814 - 1823
  • [37] A logical model for representing ambiguous states in multiple-valued logic systems
    Takagi, N
    Nakashima, K
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1999, E82D (10): : 1344 - 1351
  • [38] FAULT DETECTION FOR MULTIPLE-VALUED LOGIC CIRCUITS WITH FANOUT-FREE
    Pan Zhongliang (Dept of Physics
    Journal of Electronics(China), 2004, (05) : 376 - 383
  • [39] Smart universal multiple-valued logic gates by transferring single electrons
    Zhang, Wan-Cheng
    Wu, Nan-Jian
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2008, 7 (04) : 440 - 450
  • [40] Systematic interpretation of redundant arithmetic adders in binary and multiple-valued logic
    Homma, Naofumi
    Aoki, Takafumi
    Higuchi, Tatsuo
    IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (11): : 1645 - 1654