Benchmarking quantum logic operations relative to thresholds for fault tolerance

被引:0
|
作者
Akel Hashim
Stefan Seritan
Timothy Proctor
Kenneth Rudinger
Noah Goss
Ravi K. Naik
John Mark Kreikebaum
David I. Santiago
Irfan Siddiqi
机构
[1] University of California at Berkeley,Quantum Nanoelectronics Laboratory, Department of Physics
[2] University of California at Berkeley,Graduate Group in Applied Science and Technology
[3] Lawrence Berkeley National Lab,Computational Research Division
[4] Sandia National Laboratories,Quantum Performance Laboratory
[5] Sandia National Laboratories,Quantum Performance Laboratory
[6] Lawrence Berkeley National Lab,Materials Sciences Division
[7] Google Quantum AI,undefined
来源
npj Quantum Information | / 9卷
关键词
D O I
暂无
中图分类号
学科分类号
摘要
Contemporary methods for benchmarking noisy quantum processors typically measure average error rates or process infidelities. However, thresholds for fault-tolerant quantum error correction are given in terms of worst-case error rates—defined via the diamond norm—which can differ from average error rates by orders of magnitude. One method for resolving this discrepancy is to randomize the physical implementation of quantum gates, using techniques like randomized compiling (RC). In this work, we use gate set tomography to perform precision characterization of a set of two-qubit logic gates to study RC on a superconducting quantum processor. We find that, under RC, gate errors are accurately described by a stochastic Pauli noise model without coherent errors, and that spatially correlated coherent errors and non-Markovian errors are strongly suppressed. We further show that the average and worst-case error rates are equal for randomly compiled gates, and measure a maximum worst-case error of 0.0197(3) for our gate set. Our results show that randomized benchmarks are a viable route to both verifying that a quantum processor’s error rates are below a fault-tolerance threshold, and to bounding the failure rates of near-term algorithms, if—and only if—gates are implemented via randomization methods which tailor noise.
引用
收藏
相关论文
共 50 条
  • [1] Benchmarking quantum logic operations relative to thresholds for fault tolerance
    Hashim, Akel
    Seritan, Stefan
    Proctor, Timothy
    Rudinger, Kenneth
    Goss, Noah
    Naik, Ravi K.
    Kreikebaum, John Mark
    Santiago, David I.
    Siddiqi, Irfan
    NPJ QUANTUM INFORMATION, 2023, 9 (01)
  • [2] Volume thresholds for quantum fault tolerance
    Vaneet Aggarwal
    A. Robert Calderbank
    Gerald Gilbert
    Yaakov S. Weinstein
    Quantum Information Processing, 2010, 9 : 541 - 549
  • [3] Volume thresholds for quantum fault tolerance
    Aggarwal, Vaneet
    Calderbank, A. Robert
    Gilbert, Gerald
    Weinstein, Yaakov S.
    QUANTUM INFORMATION PROCESSING, 2010, 9 (05) : 541 - 549
  • [4] FAULT TOLERANCE IN REVERSIBLE LOGIC CIRCUITS AND QUANTUM COST OPTIMIZATION
    Arunachalam, Kamaraj
    Perumalsamy, Marichamy
    Ponnusamy, Kaviyashri K.
    COMPUTING AND INFORMATICS, 2020, 39 (05) : 1099 - 1116
  • [5] Fault tolerance in reversible logic circuits and quantum cost optimization
    Arunachalam K.
    Perumalsamy M.
    Ponnusamy K.K.
    Computing and Informatics, 2021, 39 (05) : 1099 - 1116
  • [6] Upper bounds on fault tolerance thresholds of noisy Clifford-based quantum computers
    Plenio, M. B.
    Virmani, S.
    NEW JOURNAL OF PHYSICS, 2010, 12
  • [7] OPERATIONS AND LOGIC OF QUANTUM MECHANICS
    POOL, JCT
    BULLETIN OF THE AMERICAN PHYSICAL SOCIETY, 1968, 13 (01): : 122 - &
  • [8] Fault-tolerance thresholds for code conversion schemes with quantum Reed-Muller codes
    Luo, Lan
    Ma, Zhi
    Lin, Dongdai
    Wang, Hong
    QUANTUM SCIENCE AND TECHNOLOGY, 2020, 5 (04)
  • [9] Fault Tolerance for Arithmetic and Logic Unit
    Veeravalli, Varadan Savulimedu
    PROCEEDINGS OF THE IEEE SOUTHEASTCON 2009, TECHNICAL PROCEEDINGS, 2009, : 329 - 334
  • [10] Regular array of nanometer-scale devices performing logic operations with fault-tolerance capability
    Schmid, A
    Leblebici, Y
    2004 4TH IEEE CONFERENCE ON NANOTECHNOLOGY, 2004, : 399 - 401