Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs

An efficient two-phase calibration technique for 1-bit/stage pipelined Analog–to–Digital Converters (ADCs) is presented in this paper. The proposed technique employs linear histogram testing to collect the required information to calibrate the non-ideal ADC output behavior induced by capacitor mismatch and comparator offset. In the first phase, it calibrates the missing-decision-level errors by amplification gain reduction. Unlike previous works, which require large capacitor arrays, only few switches are added to the circuit. The second phase eliminates missing-transition levels (missing codes). It achieves better calibrated linearity and provides better mismatch tolerance than the traditional digital calibration technique. Simulation results show that the proposed technique effectively improves both static and dynamic performances.