Parametric Investigation and Design of Junctionless Nanowire Tunnel Field Effect Transistor

An integrated design based on Gate-All-Around (GAA) silicon Junctionless (JL) vertical profile Nanowire (NW) structure has been proposed for JL-NW-Tunnel-Field Effect Transistor (JL-NW-TFET). A uniform high doping concentration (10−19) has been used to make the device a Junctionless structure. The parametric variations of the JL-NW-TFET have been analyzed such as ON-current (ION), OFF-current (IOFF), ON-OFF ratio of current (ION/OFF) and Subthreshold-Slope (SS). Therefore, work function of gate metal (4.4 eV to 4.8 eV), thickness of oxide (1.0 nm to 2.0 nm), diameter of Nanowire (10 nm to 30 nm) and channel length (22 nm to 65 nm) has been varied by implementing device structure in SILVACO Atlas Tools. The optimum parameters of the device have been observed as: maximum ION (3.73 × 10−6 A/μm), minimum IOFF (2.97 × 10−20 A/μm), Low SS (19.40 mV/dec) and high ION/OFF (3.35 × 1013). It has been proposed that these optimum parameter characteristics are immune to short channel effects and preferred for low power applications in nano regime.