Delay Test Generation: A Hardware Perspective

被引：0
|
作者：
Jacob Savir
机构：
[1] New Jersey Institute of Technology,ECE Dept.
来源：
Journal of Electronic Testing | 1997年 / 10卷
关键词：
delay test; linear feedback shift register; cellular automata; transition test; skewed-load delay test; shift dependency; pseudo-random test;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
An important problem one faces during design of a built-in self-test(BIST) based delay test is the selection of a proper generator toapply the test vectors. This problem is due to the need of applyinga pair of patterns to detect any given delay fault. The secondvector has to be launched against the logic immediately following thefirst vector. This timing requirement places severe restrictions onthe kind of hardware suitable for the task, especially in built-inself-test applications where the generator must reside on chip.
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页码：245 / 254
页数：9
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