Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Effect Transistor

In this paper, five layered Black Phosphorus (BP) – Silicon (Si) based Tunnel Field Effect Transistor (TFET) is used to overcome the thermionic limits faced by Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and analysis of the device validates that TFET is a better alternative as nano scale transistor. To enhance the ON state current for five layered BP-Si based TFET, multi electrode (source and drain) based structure is used. For the first time, the charge plasma technique is implemented on BP. The proper work function of metal electrodes has been selected to accordingly implement the charge plasma based technique for BP and Si. Charge plasma will result in generation of electron and hole cloud depending on the work functions at source/drain electrode. Different device properties and characteristics curves viz. IDS-VGS and IDS-VDS are compared for monolayered TFET to five layered based TFET. Different analog/RF properties, as well as linear and distortion parameters of the device such as output conductance (gd), transconductance (gm), cut-off frequency (fT), third order intermodulation distortion, second and third order harmonic distortion, second and third order voltage intercept point and current intercept point, are examined for five layered BP-Si based TFET only. For five layered BP-Si based configuration, the proposed device offers a threshold voltage of 0.42 V, an average subthreshold slope of 24.14 mV/dec, ION of 1.7 × 10−4 A/μm, Drain Induced Barrier Lowering (DIBL) of 1.02 mV/V.