Multiple Scan Chain Design for Two-Pattern Testing

被引：0

作者：

Ilia Polian

Bernd Becker

机构：

[1] Albert-Ludwigs-University,Institute of Computer Science

来源：

Journal of Electronic Testing | 2003年 / 19卷

关键词：

design for test; delay testing; scan chain insertion; core-based test;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.

引用

页码：37 / 48

页数：11

共 4 条

[1] Multiple scan chain design for two-pattern testing
Polian, I
Becker, B
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (01): : 37 - 48
[2] Multiple scan chain design for two-pattern testing
Polian, I
Becker, B
19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2001, : 88 - 93
[3] Design for hierarchical two-pattern testability of data paths
Altaf-Ul-Amin, M
Ohtake, S
Fujiwara, H
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2002, E85D (06): : 975 - 984
[4] Design for two-pattern testability of controller-data path circuits
Altaf-Ul-Amin, M
Ohtake, S
Fujiwara, H
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2003, E86D (06) : 1042 - 1050

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