Variability in nanoscale CMOS technology

被引:0
作者
Kelin Kuhn
机构
[1] Intel Corporation,Portland Technology Development
来源
Science China Information Sciences | 2011年 / 54卷
关键词
CMOS; variation; SRAM;
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学科分类号
摘要
Moore’s Law technology scaling has improved VLSI performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore’s Law, a variety of challenges will need to be overcome. One of these challenges is management of process variation. This paper discusses the importance of process variation in modern CMOS transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques (including circuit and SRAM data from the 32 nm node), and compares recent intrinsic transistor variation performance from the literature.
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[1]  
Kuhn K.(2008)Managing process variation in intel’s 45 nm CMOS technology Intel Tech J 12 93-110
[2]  
Kenyon C.(2003)Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness IEEE Trans Electr Dev 50 1254-1260
[3]  
Kornfeld A.(2001)Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation introduced by tunnelling leakage current IEEE Trans Electr Dev 48 259-264
[4]  
Asenov A.(2006)Estimation of fixed charge densities in hafnium-silicate gate dielectrics IEEE Trans Electr Dev 53 2627-2633
[5]  
Kaya S.(2006)On oxygen deficiency and fast transient charge-trapping effects in high-k dielectrics IEEE Electr Dev Lett 27 984-987
[6]  
Brown A. R.(1998)Modeling statistical dopant fluctuations in MOS transistors IEEE Trans Electr Dev 45 1960-1971
[7]  
Koh M.(1998)Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET’s: A 3-D “atomistic simulation study” IEEE Trans Electr Dev 45 2505-2513
[8]  
Mizubayashi W.(2007)Modeling of the threshold voltage in strained Si/Si1-x GexSi1-yGex CMOS architectures IEEE Trans Electr Dev 54 3040-3048
[9]  
Iwamoto K.(2009)Measurement and analysis of variability in 45 nm strained-Si CMOS technology IEEE J Solid State Circ 44 2233-2243
[10]  
Kaushik V. S.(2007)Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture IEEE Trans Electr Dev 54 3056-3063