Scalable high voltage CMOS technology for smart power and sensor applications

被引：2

作者：

Schrems M. ^{[1
]}

Knaipp M. ^{[1
]}

Enichlmair H. ^{[1
]}

Vescoli V. ^{[1
]}

Minixhofer R. ^{[1
]}

Seebacher E. ^{[1
]}

Leisenberger F. ^{[1
]}

Wachmann E. ^{[1
]}

Schatzberger G. ^{[1
]}

Gensinger H. ^{[1
]}

机构：

[1] Austriamicrosystems, 8141 Unterpremstätten

来源：

e & i Elektrotechnik und Informationstechnik | 2008年 / 125卷 / 4期

关键词：

CMOS; Design flow; Device reliability; Embedded NVM; ESD; High voltage; HV-CMOS; Integrated circuits; Process design kits; Smart power;

D O I：

10.1007/s00502-008-0519-y

中图分类号：

学科分类号：

摘要：

Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded non-volatile memory. In this work we propose a new 0.35 μm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 μm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 °C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM/Flash technology is shown. We also provide first verification results of the scalability of the proposed 0.35 μm HVCMOS technology to 0.18 μm and beyond as well as to currents of up to 8 A. © 2008 Springer-Verlag.

引用

页码：109 / 117

页数：8

共 16 条

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